The invention relates to a circuitry system that comprises synchronous clock domains of a streaming data bus. The invention also relates to a method for connecting synchronous clock domains of such a circuitry system.
When building large Systems-on-a-Chip (SoCs), for example for use in mobile communication applications, designers will combine several IP blocks, also known as IP (intellectual property) cores, even possibly from different vendors, via well-defined bus interfaces.
A design requirement especially for mobile systems, but not restricted thereto, is to support clock-gating on a per-design-block (i.e. per-IP) basis to save power and increase battery life. In the case of an SoC for wireless communication applications, these building blocks are the various components of the system, such as for example a digital front end (DFE), a Tx unit, a shared RAM, a forward error correction (FEC) data unit, a fast Fourier transform (FFT) unit, a parameter estimation unit, equalizer unit, searcher unit, an FEC control unit and the like, which components include several data processing units and a local embedded controller. When gating off one block's clock, however, it must be made sure that the busses crossing the block boundaries will not violate their protocols, and will not suffer from data loss or integrity issues.
Since a bus between two blocks that belong to separate clock domains creates interdependency between these two clock domains, ensuring protocol consistency of this bus involves contribution from both clock domains. This also means that each clock domain, i.e. the respective local controller thereof, must know the gating state of the other domain. Conventionally, to go into a clock-off state for one domain required the following steps:                determining that the local block is in some form of idle state and all communication across the bus has ceased        informing the other block about the intention to switch off the local clock, so that the bus will not be activated during the clock-off period        receiving the confirmation from the other block        switching off the local clock        
It will be understood that this approach not only involves both sides of the bus, but also a higher protocol level than that of the bus itself. That means that both local controllers must actively process information about the clock state, hence software is involved. If one side of the bus wants to re-activate the bus, it must again carry out a similar protocol to make sure both sides have their clocks running, before actually transferring data over the bus.
It is an object of the invention to minimize system and software complexity of SoCs. A particular object of the invention is to provide means which allow two building blocks of an SoC to switch their clocks on and off independently while avoiding data loss and protocol violation.